This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-193519, filed Jun. 26, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device using an SOI (Silicon On Insulator) substrate and a method of manufacturing the same and, more particularly, to the structure of a trench capacitor.
2. Description of the Related Art
The integration degree of a semiconductor integrated circuit has been improved year by year, and in particular, the integration degree of a memory circuit makes remarkable progress. For example, since a DRAM (Dynamic Random Access Memory) cell comprised of one transistor and one capacitor is required for an increase in integration degree and a decrease in manufacturing cost, an area occupied by components needs to be reduced. However, when the area and width of a resistive element need to be made smaller along with DRAM cell downsizing, it is difficult to maintain the electrical characteristics. To solve this, a trench capacitor capable of reducing the occupied area and maintaining the electrical characteristics is proposed.
FIGS. 32 to 38 are sectional views showing the steps in manufacturing a semiconductor memory device having a trench capacitor according to the prior art. A method of manufacturing the semiconductor memory device according to the prior art will be briefly described below.
As shown in FIG. 32, an SOI (Silicon On Insulator) substrate 111 is formed first. The SOI substrate 111 is formed from first and second semiconductor layers 111a and 111b and a buried layer 111c which is made of, e.g., an SiO2 film and formed between the first and second semiconductor layers 111a and 111b. An SiO2 film 112 is formed on the SOI substrate 111, and an SiN film 113 is formed on the SiO2 film 112. A trench 117 is then formed to reach the first semiconductor layer 111a through the SiN film 113, SiO2 film 112, second semiconductor layer 111b, and buried layer 111c. 
An AsSG (Arsenic Silicate Glass) film 118 is formed on the inner side and bottom surfaces of the trench 117 and on the SiN film 113. The portion of the AsSG film 118 is removed by isotropic etching using a hydrofluoric acid solution. As in the AsSG film 118 is diffused into the first semiconductor layer 111a at the outer side surface of the trench 117 by high-temperature annealing. With this process, a plate diffusion layer 121a serving as a capacitor electrode is formed in the first semiconductor layer 111a along the side and bottom surfaces of the trench 117. The AsSG film 118 is then removed.
As shown in FIG. 33, a capacitor insulating layer 122 is formed on the inner side and bottom surfaces of the trench 117 and on the SiN film 113, and a polysilicon film 123 with As serving as a prospective capacitor electrode is formed on the capacitor insulating film 122. The polysilicon film 123 and capacitor insulating film 122 are removed so as to leave them inside the trench 117 in the first semiconductor layer 111a. With this process, a trench capacitor 127 formed from the plate diffusion layer 121a, capacitor insulating layer 122, and polysilicon film 123 is formed in the trench 117 in the first semiconductor layer 111a. A TEOS film 124 is then formed on the polysilicon film 123 and the side surface of the trench 117 at the second semiconductor layer 111b and buried layer 111c. 
As shown in FIG. 34, a polysilicon film 126 containing As is formed in the trench 117 and on the SiN film 113.
As shown in FIG. 35, the polysilicon film 126 is removed by anisotropic etching such that its upper surface has a lower level than that of the second semiconductor layer 111b. 
As shown in FIG. 36, the TEOS film 124 is removed by anisotropic etching such that its upper surface has lower level than that of the polysilicon film 126.
As shown in FIG. 37, a polysilicon film 140 containing As is formed in the trench 117 and on the SiN film 113.
As shown in FIG. 38, the polysilicon film 140 is removed by anisotropic etching such that its upper surface has a lower level than that of the second semiconductor layer 111b. 
In this fashion, a transistor connection portion 128 formed from the polysilicon films 126 and 140 is formed and electrically connected to the trench capacitor 127.
In the prior art described above, when the AsSG film 118 is removed by isotropic etching using a hydrofluoric acid solution, the buried layer 111c and SiO2 film 112 retreat in the lateral direction, thus undesirably forming recessed portions 130a and 130b, as shown in FIG. 32. With this structure, when the trench 117 is filled with the polysilicon film 126, a gap 141 is generated in the region in the trench 117 in which the recessed portion 130a is present, as shown in FIG. 34.
This causes a decrease in sectional area of the connection portion 128 serving as the current path between the capacitor 127 and a transistor (not shown). Therefore, since a parasitic resistance as the DRAM cell increases, the memory cannot realize high-speed read/write of an electrical signal as a DRAM element.
A semiconductor memory device according to a first aspect of the present invention comprises a first semiconductor layer, a buried insulating layer formed on the first semiconductor layer, a second semiconductor layer formed on the buried insulating layer, a trench formed to reach the first semiconductor layer through the second semiconductor layer and the buried insulating layer, the trench comprising a retreated portion at which a side surface of the buried insulating layer retreats with respect to a side surface of the second semiconductor layer, and the trench defining a first opening width at the second semiconductor layer, a first capacitor electrode formed in the first semiconductor layer along a side surface and a bottom surface of the trench, a capacitor insulating film formed in the trench to cover the first capacitor electrode, a second capacitor electrode formed in the trench in the first semiconductor layer to oppose the first capacitor electrode through the capacitor insulating film, an insulating film formed on a side surface of the retreated portion, the insulating film defining a second opening width and a third opening width, the second opening width serving as a width at the buried insulating layer, the second opening width being not more than the first opening width, and the third opening width serving as a width at a boundary portion between the buried insulating layer and first semiconductor layer, and a connection portion which is formed in the trench in the buried insulating layer and the second semiconductor layer and electrically connected to the second capacitor electrode.
A semiconductor memory device according to a second aspect of the present invention comprises a first semiconductor layer, a buried insulating layer formed on the first semiconductor layer, a second semiconductor layer formed on the buried insulating layer, a trench formed to reach the first semiconductor layer through the second semiconductor layer and the buried insulating layer, an insulating film formed on a side surface of the trench at a level lower than an upper surface of the second semiconductor layer, a first capacitor electrode formed on the insulating film and a bottom surface of the trench, a capacitor insulating film formed in the trench to cover the first capacitor electrode, a second capacitor electrode formed in the trench to oppose the first capacitor electrode through the capacitor insulating film, and a connection portion which is formed in the trench in the second semiconductor layer and electrically connected to the second capacitor electrode.
A method of manufacturing a semiconductor memory device according to a third aspect of the present invention comprises forming a substrate, the substrate comprising a buried insulating layer formed on a first semiconductor layer and a second semiconductor layer formed on the buried insulating layer, forming a trench to reach the first semiconductor layer through the second semiconductor layer and the buried insulating layer, forming a first insulating film, which contains an impurity, on a side surface and a bottom surface of the trench, removing the first insulating film by isotropic etching on the side surface of the trench at the second semiconductor layer and the buried insulating layer, diffusing the impurity into the first semiconductor layer and forming a first capacitor electrode of a diffusion layer along the side surface and the bottom surface of the trench, removing the first insulating film, forming a capacitor insulating film on the side surface and the bottom surface of the trench in the first semiconductor layer, forming a second capacitor electrode on the capacitor insulating film, forming a second insulating film from the side surface of the trench at the buried insulating layer to a portion of an upper surface of the second capacitor electrode, and forming a connection portion in the trench in the second semiconductor layer and the buried insulating layer and electrically connecting the connection portion to the second capacitor electrode.
A method of manufacturing a semiconductor memory device according to a fourth aspect of the present invention comprises forming a substrate, the substrate comprising a buried insulating layer formed on a first semiconductor layer and a second semiconductor layer formed on the buried insulating layer, forming a trench to reach the first semiconductor layer through the second semiconductor layer and the buried insulating layer, forming an insulating film on a side surface of the trench, forming a first capacitor electrode on the insulating film and a bottom surface of the trench at a level lower than an upper surface of the second semiconductor layer, forming a capacitor insulating film on the first capacitor electrode and the insulating film, forming a second capacitor electrode on the capacitor insulating film in the trench, removing the second capacitor electrode, the capacitor insulating film, and the insulating film and exposing a portion of a side surface of the second semiconductor layer, and forming a connection portion in the trench in the second semiconductor layer and electrically connecting the connection portion to the second capacitor electrode.